On Fri, 8 Sep 2000, Justin Schoeman wrote: > The byte enables are more-or-less automatic. All writes are DWORD > aligned, but the output of the FIFO has some automated logic to decide > which byte addresses to actually modify. At least I assume this is so, > because I never implemented byte enables, but the stippel test worked > (in 8, 16 and 24 bpp modes - my X server didn't want to do 32bpp). After thinking about it more, I see how this can be so. By looking at the two low order bits if the DMA destination address register, the DMA controller could easily figure out which bytes to disable, just as it does by looking at the FIFO status code at the end of the line. Depending on exactly what the bt848 does, using WRITE instructions with non-aligned destination addresses will either not work at all, or not work as expected. Since the V4L1 driver doesn't use WRITEC, and just WRITE, it doesn't work right with byte wide overlay. If the driver used WRITEC instuctions, it should work without any special work. Of course the Bt848 has a limit to the rate at which it can process RISC commands, from lack of PCI bandwidth if nothing else.
